What's the tradeoff between PWM frequency and duty-cycle resolution?

They trade off because the same ARR value sets both. The number of distinct duty steps is ARR+1 (duty resolution = 1/(ARR+1)), and the frequency is f_clk/((PSC+1)(ARR+1)). From a fixed timer clock, raising the PWM frequency requires lowering ARR (fewer counter ticks per period), which directly reduces the number of duty steps. For example, at 72 MHz an ARR of 7199 gives 10 kHz with ~7200 steps (almost 13-bit resolution), while an ARR of 71 gives 1 MHz with only 72 steps (~6-bit). So you cannot independently maximize both frequency and resolution from a given clock, you pick the frequency the load demands (above flicker/audible thresholds, below switching-loss limits) and accept the resulting resolution, or you raise the timer clock to buy back steps. This matters when, say, you need both high-frequency motor drive and fine speed control and discover the resolution is too coarse.