What is dead-time in a complementary PWM pair, and why does an H-bridge need it?

An H-bridge (or half-bridge) leg has a high-side and a low-side switch in series across the supply, driven by complementary PWM: when one is on the other is off. The danger is that real MOSFETs don't switch instantly, turn-off takes finite time (gate charge, Miller plateau), so if you command the low-side on the instant you command the high-side off, both are momentarily conducting and you get shoot-through: a direct short from rail to ground through both transistors, which spikes current and can destroy the FETs. Dead-time is a small deliberate gap inserted between one switch turning off and its complement turning on, so both are guaranteed off during the transition. Advanced timers generate it in hardware (e.g. STM32's TIM1/TIM8 have a dead-time generator with a programmable DTG field on the complementary outputs), which is far more reliable than trying to space the edges in software. The tradeoff is that dead-time slightly distorts the output waveform, longer dead-time is safer but introduces more duty-cycle error, so you set it just long enough to cover the worst-case switch turn-off plus gate-driver propagation delay.