Atomicity. Setting a pin with ODR |= (1<<n) is a read-modify-write: the CPU loads ODR, ORs in the bit, and stores it back, three separate operations. If an interrupt fires between the load and the store and modifies the same port, the ISR's change sits in the register when the interrupted code writes back its stale-plus-modified value, silently wiping the ISR's update, a classic data race. The BSRR (bit set/reset register) eliminates this: writing a 1 to a low-half bit sets the corresponding pin and writing a 1 to the matching high-half bit resets it, all in a single store with no read involved, so there's nothing for an interrupt to interleave with. It's atomic by construction, needs no critical section, and is faster (one instruction). So for any GPIO that an ISR and main code might both touch, BSRR is the correct choice over RMW on ODR.
Embedded Systems Fundamentals · Interview question
What's the advantage of a bit set/reset register (like BSRR) over read-modify-write on the output register?
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Registers & Memory-Mapped I/O
How writing a memory address turns on an LED: control/status/data registers, the volatile register-overlay struct, and the write-1-to-clear and atomic set/reset traps.