They define the clock's idle state and sampling timing, and both ends must match. CPOL (clock polarity) sets whether the clock idles low (0) or high (1). CPHA (clock phase) sets whether data is sampled on the first clock edge of each bit or the second. The four combinations are SPI modes 0 through 3. The slave's datasheet fixes which mode it requires; the master must be configured identically. If they disagree, the master latches the data line on the wrong edge, either half a bit early or late, so it reads bit-shifted or garbled values, often looking like every byte is rotated or consistently wrong. It's the single most common SPI bring-up bug, and because the symptom is "consistent garbage," people often chase wiring when the real fix is matching the mode (frequently mode 0 or mode 3). The debugging move is to scope SCLK and the data line to see the idle level and which edge the slave drives/expects, then set the master's CPOL/CPHA to match.
Communication Protocols · Interview question
What are CPOL and CPHA, and what happens if they're wrong?
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From the lesson
SPI
The fast 4-wire synchronous bus: a master-driven clock, full-duplex shift registers (to read you write), chip-select per device, and the CPOL/CPHA modes both ends must match.