SPI links the master and the selected slave as two 8-bit shift registers connected in a ring: MOSI carries bits from the master's register to the slave's, and MISO carries bits from the slave's register back to the master's, both driven by the master's clock. On each of 8 clock edges one bit moves each direction simultaneously, so after 8 clocks the two registers have completely swapped their bytes, every transfer is inherently bidirectional. The consequence is that there's no separate "read" operation: to clock a byte out of the slave you must clock a byte into it, because the same edges drive both shifts. So to read data you write a dummy byte (commonly 0x00 or 0xFF) whose only purpose is to generate the 8 clocks, and you keep the byte the slave shifted back. Likewise, when you only care about sending, you discard whatever the slave returns. This "to read, you write" property surprises people coming from buses with distinct read/write transactions.
Communication Protocols · Interview question
Explain SPI's full-duplex shift-register model. Why do you "write to read"?
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From the lesson
SPI
The fast 4-wire synchronous bus: a master-driven clock, full-duplex shift registers (to read you write), chip-select per device, and the CPOL/CPHA modes both ends must match.