SPI has no addressing in the protocol itself, the master selects which device participates by asserting that device's chip-select (CS, active-low) line low for the duration of the transaction and releasing it high afterward. All devices share SCLK, MOSI, and MISO, but only the device whose CS is low listens and drives MISO; the rest must keep their MISO outputs tri-stated (high-impedance) so they don't contend with the selected one. The cost is one dedicated CS GPIO per slave, so pin count scales with the number of devices, three slaves means three CS lines plus the three shared signals. There's also a daisy-chain mode for some device families where data shifts through devices in series using a single CS, but it's less common and device-specific. Compared to I2C, which addresses many devices over just two shared wires, SPI trades pins for speed and simplicity, no addressing overhead means lower latency and higher throughput, at the price of wiring.
Communication Protocols · Interview question
How does SPI address multiple devices, and what's the cost?
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From the lesson
SPI
The fast 4-wire synchronous bus: a master-driven clock, full-duplex shift registers (to read you write), chip-select per device, and the CPOL/CPHA modes both ends must match.