On-Chip Debugging: JTAG & SWD

How GDB physically reaches into a running chip: built-in debug logic accessed via JTAG (4-5 pins) or ARM's 2-pin SWD, through a debug probe, enabling halt/run, memory access, flashing, and trace.

22 min read

In this lesson:

what on-chip debugging is and the host→probe→chip chain
JTAG (4-5 pins) vs SWD (2 pins), and why SWD dominates ARM
what the debug port enables (halt/run, memory, breakpoints, flash, trace)
SWO trace for printf/profiling
the gotchas: probe choice, VTref, and locking yourself out

The previous lesson connected GDB to a target "over a port." This is the hardware underneath that.

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