Why is 1-Wire timing tricky on a microcontroller, and how do you handle it?

1-Wire encodes bits purely in the duration of low pulses on a microsecond scale, for instance a write-0 holds the line low for most of a ~60 µs slot while a write-1 is a brief low then release, and a read samples the line at a precise instant after a short low. Because the information is in the timing, anything that delays the master mid-slot corrupts the bit: if an interrupt fires while you're holding the line low and stretches that low by even tens of microseconds, a 1 can look like a 0 or the slave mis-times its response, and there's no clock or handshake to recover, the bit is just wrong. So the core problem is that 1-Wire bit-banging has hard real-time constraints that ordinary interrupt activity violates. The handling options: disable interrupts (a critical section) around each time slot so nothing can stretch a pulse, simple but it adds interrupt latency you must budget; use a hardware timer or a clever UART trick (configuring a UART's bit timing to generate the precise low pulses) so the timing is generated by hardware and is immune to CPU jitter; or use a dedicated 1-Wire master peripheral/bridge chip if available. You also size the pull-up correctly and apply a strong pull-up during high-current operations. The general lesson is that timing-critical bit-banged protocols don't tolerate the jitter of a normally-running interrupt system, so you either lock out interrupts briefly or push the timing into hardware.