What's your general method for debugging a misbehaving bus?

Measure before theorizing, because most comm failures are physical-layer and no amount of code reading reveals a swapped wire or a missing resistor. Step one is to put a scope or logic analyzer on the bus and actually look: idle levels, edge quality, the bit period, ACKs, chip-select timing, this resolves the majority of bus bugs immediately. Step two, confirm power and a true common ground to every device. Step three, verify timing against the actual peripheral clock, not the configured number, measure a bit width on the scope and compare. Step four, for open-drain buses check the pull-ups and idle levels. Step five, isolate and bisect: reduce to a single device, slow the bus down until it works, then add devices and speed back one change at a time so you can attribute any failure to a specific variable. Throughout, use the consistent-vs-intermittent distinction to steer, consistent corruption means deterministic timing/format mismatch, intermittent means analog (noise, grounding, contention, marginal pull-ups/termination). The anti-patterns to avoid are assuming the bug is in software, changing several things at once, and trusting the configured settings instead of measuring what's actually on the wire.