A bus works at low speed but fails when you increase the clock rate. What's going on?

Rising speed exposes analog limits that were hidden when bit periods were long. On I2C the prime suspect is the pull-ups combined with bus capacitance: each rising edge is an RC charge curve, and if the pull-up is too weak (resistance too high) or the bus has too much capacitance (long traces, many devices), the line can't rise to a valid high within the now-shorter bit time, so edges round off and the receiver mis-samples, lowering the pull-up resistance or shortening/unloading the bus fixes it. On CAN the suspect is termination and reflections: at higher bit rates the signal must settle within a smaller window, so missing or wrong termination (reflections) that were tolerable slowly now cause bit errors. Generally, any marginal signal-integrity issue, weak drive, capacitance, reflections, inadequate slew, scales with speed because the timing margin shrinks. The debugging approach is to scope the edges at the failing speed (look for slow/rounded rising edges or ringing), then address the physical cause (pull-up value, capacitance, termination) rather than just backing the speed off permanently.