What's the correct sequence to switch the system clock to a PLL running off an external crystal?

Order matters at every step. First, enable the external crystal oscillator (HSE) and poll its ready flag until it's stable, using it before it's settled hangs the core. Second, before going to high speed, set the flash wait states (latency) appropriate for the target frequency, because the faster clock needs more wait states or the core will fetch invalid instructions. Third, configure the PLL, select HSE as its source and set the multiplier (and any pre/post dividers) for the target frequency, then enable it and poll its lock flag. Fourth, set the AHB and APB prescalers so that no bus exceeds its maximum rated frequency at the new SYSCLK. Fifth, switch the SYSCLK mux to the PLL and poll the status bits until the hardware confirms the switch has taken effect. Optionally enable the clock security system to fall back if the crystal fails. The two rules that catch people: flash wait states before the speed increase, and wait for ready/lock after enabling each oscillator and the PLL before depending on it. Vendor HAL/CubeMX generates this sequence, but understanding it is essential for debugging or bare-metal bring-up.