What does the PLL do in the clock tree?

A PLL (Phase-Locked Loop) multiplies a clock frequency up: you feed it a modest, stable input, say an 8 MHz crystal or the internal RC, and it generates a much higher output, like 72, 168, or 480 MHz, that the core runs from. This lets you get both stability and speed: a slow crystal is cheap and accurate, and the PLL scales it to the high frequency the CPU needs, rather than requiring an expensive high-frequency crystal. The output follows the input's accuracy, so a crystal-driven PLL is precise while an RC-driven PLL inherits the RC's drift. The PLL takes time to lock after you enable it, so you must wait for its ready/lock flag before switching the system clock to it. In the tree, the PLL output is one of the selectable SYSCLK sources, and it's the one you almost always pick for full-speed operation, with the AHB/APB prescalers then dividing it back down for the buses and peripherals.