What is the MAC/PHY split and why does it matter on an MCU?

An Ethernet interface is divided into two functional blocks. The MAC (Media Access Control) is the digital half: it builds and parses frames, handles MAC addressing and the frame-check sequence, and implements the access rules, on many MCUs this is an on-chip Ethernet MAC peripheral. The PHY (physical layer) is the analog half: it converts frame bits into the actual electrical signaling on the twisted pair, does the line coding, and negotiates link speed and duplex, it's almost always a separate chip. They connect over a standard interface, MII or the reduced-pin RMII, and the MAC configures the PHY through a management bus called MDIO. This matters on embedded because a typical design pairs the MCU's integrated MAC with an external PHY over RMII, so bring-up requires getting the RMII reference clock right (commonly 50 MHz for RMII), matching the PHY's MDIO address to what the driver expects, and providing the magnetics (isolation transformer) and RJ45, and missing any of those (wrong clock, wrong PHY address) gives "no link" with otherwise-correct software. Understanding the split tells you whether a problem is in your frame/IP software (MAC side and up) or in clocking/PHY/cabling (PHY side and down).