In this lesson:
- Ethernet as the Link layer (L2): frames and MAC addresses
- the Ethernet frame format and the 1500-byte MTU
- the MAC vs PHY split, and how MCUs wire them (RMII)
- how a switch forwards by MAC (vs an old hub)
- auto-negotiation, duplex mismatch, and the embedded gotchas
The local-delivery layer
Ethernet is the dominant Link-layer (OSI layer 2) technology, it moves frames between devices on the same local network (LAN). Above it sits IP (which addresses across networks); Ethernet handles delivery within a link using MAC addresses.
A MAC address is a 48-bit hardware address, usually globally unique: the top 24 bits are the manufacturer (OUI), the bottom 24 identify the device. Written AA:BB:CC:DD:EE:FF. Every Ethernet interface has one, and frames carry a source and destination MAC for local delivery.
The Ethernet frame
┌──────────┬──────────┬──────────┬───────────┬──────────────┬──────┐
│ Preamble │ Dest MAC │ Src MAC │ EtherType │ Payload │ FCS │
│ (7+1) │ (6) │ (6) │ (2) │ 46 – 1500 │ (4) │
└──────────┴──────────┴──────────┴───────────┴──────────────┴──────┘
│ │ │
e.g. 0x0800 = IPv4 the data CRC-32 check- Dest/Src MAC, who it's for, who sent it (local link only).
- EtherType, what's inside (0x0800 = IPv4, 0x0806 = ARP, 0x86DD = IPv6).
- Payload, 46-1500 bytes; 1500 is the standard MTU (Maximum Transmission Unit). An IP packet must fit here or be fragmented.
- FCS, a CRC-32 the receiver checks; a corrupted frame is dropped (no retransmission at this layer, that's TCP's job).
MAC vs PHY: two halves of the interface
An Ethernet port is split into two blocks, a distinction that matters constantly on embedded:
- MAC (Media Access Control), the digital half: builds/parses frames, handles addressing, FCS, and the access rules. Often integrated into the MCU (an Ethernet MAC peripheral).
- PHY (Physical layer), the analog half: turns frame bits into the actual electrical signaling on the twisted pair, handles line coding, and negotiates speed/duplex. A separate chip.
They connect over a standard interface, MII or the reduced RMII (fewer pins). Beyond the PHY you also need magnetics (a transformer for isolation) and the RJ45 jack.
MCU ─[ Ethernet MAC ]─(R)MII─[ PHY chip ]─[ magnetics ]─[ RJ45 ]─ cable
digital: frames analog: signaling, speed/duplexSo a typical MCU Ethernet design is: on-chip MAC + external PHY over RMII, configured via the MDIO management bus, with lwIP running the IP/TCP layers on top.
Switching: forwarding by MAC
Old hubs were dumb, every bit in one port went out all ports (one shared collision domain). A switch is smart: it learns which MAC address lives on which port (by watching source MACs), then forwards each frame only to the port where the destination lives.
flowchart LR
A[Host A<br/>MAC AA] --- SW[Switch<br/>learns MAC↔port]
B[Host B<br/>MAC BB] --- SW
C[Host C<br/>MAC CC] --- SW
SW -. "frame to BB → only B's port" .-> BThis means each switch port is its own collision domain, so modern full-duplex switched Ethernet has no collisions at all. (The old half-duplex shared medium used CSMA/CD, carrier sense, collision detect, back off, which is now historical for wired Ethernet.) Broadcasts (destination FF:FF:FF:FF:FF:FF) still go to every port, the broadcast domain.
Gotchas
- Set a valid, unique MAC. Don't ship devices with a duplicate or all-zero MAC, two identical MACs on one LAN break delivery. Use your assigned OUI, a chip's built-in MAC, or a locally administered address (the L bit set) for prototypes.
- MTU = 1500. A payload over 1500 bytes is fragmented by IP (or rejected if "don't fragment"). Oversized writes and path-MTU issues cause stalls; keep messages within the MTU where possible.
- Auto-negotiation / duplex mismatch. The PHY negotiates speed and duplex with its link partner. If one end is forced and the other auto-negotiates, you can get a duplex mismatch, the link "works" but throughput collapses under load with errors. Let both ends auto-negotiate, or force both.
- MAC↔PHY config. RMII needs the right reference clock, the PHY's address must match what the driver expects (MDIO), and the magnetics/RJ45 must be correct. A wrong PHY address or missing 50 MHz RMII clock = no link, a classic Ethernet bring-up failure.
- FCS errors point at the physical layer. Frequent CRC/FCS errors mean cabling, magnetics, or PHY/signal-integrity problems, not your software.
TL;DR
- Ethernet is the Link layer (L2): it delivers frames between devices on the same LAN using 48-bit MAC addresses (source + destination per frame).
- The frame is dest MAC | src MAC | EtherType | payload (46-1500, MTU=1500) | FCS (CRC-32); a bad FCS is dropped (reliability is left to TCP above).
- An interface splits into MAC (digital: framing/addressing, often on-chip) and PHY (analog: signaling, speed/duplex, a separate chip), joined by (R)MII and configured over MDIO, plus magnetics and an RJ45.
- A switch learns MAC→port and forwards frames only where needed, so full-duplex switched Ethernet has no collisions (CSMA/CD is the historical shared-medium scheme).
- Embedded gotchas: assign a valid unique MAC, respect the 1500 MTU, avoid duplex mismatch (auto-negotiate both ends), and get the RMII clock / PHY address right or you get no link.