Communication Protocols · Interview question

What is clock stretching?

A strong answer

Clock stretching is how a slave tells the master "wait, I'm not ready." Because SCL is open-drain, a slave can hold SCL low after a byte even though the master has released it; the master, monitoring SCL, sees that it hasn't risen and pauses its clocking until the slave releases it. This lets a slow device, say a sensor that needs to finish a conversion, or a microcontroller-based slave servicing the request in software, pace the master without losing data, which is valuable since the master otherwise sets the clock unilaterally. The catch is interoperability: not every master implements stretching correctly (some hardware I2C peripherals have errata around it, and naive bit-banged masters may ignore SCL state), so if a device relies on stretching and the master doesn't honor it, the master reads stale or garbage data because it clocked ahead before the slave was ready. So when using a device that stretches, you verify the master supports it, and it's a known source of subtle, device-specific bugs.

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From the lesson

I2C

Many devices on two wires: open-drain SDA/SCL with pull-ups, 7-bit addressing, ACK/NACK handshaking, clock stretching, and why a missing pull-up is the classic I2C failure.

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