It's a write-then-read framed by START/STOP with a repeated START in the middle. The master issues a START (SDA low while SCL high) to claim the bus, then sends the 7-bit device address with the R/W bit set to write; the addressed slave pulls SDA low on the ninth clock to ACK. The master sends the register pointer/address byte, which the slave ACKs. Now, instead of a STOP, the master issues a repeated START, keeping ownership of the bus so no other master can interleave, and re-sends the device address, this time with the R/W bit set to read; the slave ACKs and then drives the requested data byte(s) onto SDA, MSB-first. For each byte the master wants to continue reading it ACKs; on the final byte it sends a NACK to tell the slave to stop driving, then issues a STOP to release the bus. The repeated START is important because it makes the "set the register pointer, then read it" an atomic transaction. In firmware you'd drive the MCU's I2C peripheral and check its status flags at each step, but the wire sequence is exactly this.
Communication Protocols · Interview question
Walk through how a master reads a register from an I2C device.
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I2C
Many devices on two wires: open-drain SDA/SCL with pull-ups, 7-bit addressing, ACK/NACK handshaking, clock stretching, and why a missing pull-up is the classic I2C failure.
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Why does I2C use open-drain lines with pull-up resistors?What is clock stretching?You put two of the same sensor on an I2C bus and one doesn't respond. Why?The whole I2C bus is dead, SDA or SCL stuck. How do you diagnose it?What are the I2C bus speed modes, and what limits how fast you can actually run the bus?
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