The NVIC (Nested Vectored Interrupt Controller) is the Cortex-M block that manages all interrupts, with three core jobs. Vectoring: each interrupt source has an entry in the vector table, an array of handler addresses, and the NVIC dispatches directly to the correct ISR with no software polling of "who interrupted." Prioritization: each interrupt has a configurable priority, so when multiple are pending the most urgent runs first (and on Cortex-M, lower priority number means higher urgency). Nesting/preemption: a higher-priority interrupt can preempt an ISR that's already executing, run to completion, and then return to the preempted one, this is the "nested" in the name. You interact with it by enabling/disabling sources and setting their priorities (e.g., NVIC_EnableIRQ, NVIC_SetPriority). The NVIC also coordinates with the core's automatic context save/restore, which is why ISRs can be plain C functions.
Embedded Systems Fundamentals · Interview question
What does the NVIC do?
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Interrupts & ISRs
Let hardware tap the CPU on the shoulder instead of polling: the NVIC, the vector table, interrupt latency, and the hard rules for writing a correct ISR.