Pro lesson · Preview

Interrupts & ISRs

Let hardware tap the CPU on the shoulder instead of polling: the NVIC, the vector table, interrupt latency, and the hard rules for writing a correct ISR.

25 min read

This lesson is part of Pro

Upgrade to unlock the full lesson and the complete interview Q&A.

Unlock with Pro

5 interview questions on this topic

Each one opens a full worked answer.

Why use interrupts instead of polling?What does the NVIC do?What are the rules for writing a good ISR?What happens if an ISR doesn't clear its interrupt flag?Why must a variable shared between an ISR and main code be volatile, and is volatile enough?

This is just the start

Sign up free to track your progress through this course, mark lessons complete, and work through the full interview Q&A.

Sign up freeSee pricing

More in Embedded Systems Fundamentals

What Is an Embedded System?Inside an MCUThe Memory Map
Registers & Memory-Mapped I/O
GPIO: Digital I/O
Timers & Counters
Interrupts & ISRs | EmbeddedPrep.io