They're the internal bus hierarchy on ARM Cortex-M MCUs. AHB (Advanced High-performance Bus) is the fast backbone connecting the CPU core, memory (flash/SRAM), the DMA controller, and high-bandwidth peripherals. APB (Advanced Peripheral Bus) is a slower bus, often split into APB1 and APB2, that hangs off the AHB and serves lower-speed peripherals like basic timers, UARTs, and I²C. This hierarchy matters for two practical reasons: each bus has its own clock prescaler in the clock tree, so a peripheral's actual clock frequency depends on which bus it's on (get that wrong and your timer/baud-rate math is off), and the buses have finite bandwidth, so the CPU and DMA can contend for the same bus and stall each other under heavy traffic. The datasheet groups peripherals and their register base addresses by bus for exactly this reason.
Embedded Systems Fundamentals · Interview question
What are AHB and APB?
A strong answer
What a weak answer sounds like
You know the answer. Do you know what gets you dinged?
Pro breaks down the answer most candidates actually give to this question — and the specific reason an interviewer marks it down. It’s the difference between sounding correct and sounding senior, on all 472 questions.
From the lesson
Inside an MCU
The block diagram demystified: a CPU core, flash and SRAM, and peripherals wired together by internal buses, and why peripherals working in parallel with the CPU is the whole point.