How does pin count scale differently across the three buses as you add devices?

Very differently, and it often decides the design. I2C is flat: all devices share the same two lines (SDA, SCL), and selection is by address, so going from 2 devices to 10 adds zero pins (only address space, which is finite). SPI grows by one pin per device: SCLK, MOSI, and MISO are shared, but each slave needs its own chip-select, so N slaves cost N CS GPIOs on top of the three shared lines. UART is inherently point-to-point, one TX/RX pair links exactly two endpoints, so N modules need N UART peripherals (or external muxing), and MCUs have a limited number of UART instances. So on a pin-constrained MCU, I2C scales best for many devices, SPI is fine for a handful, and UART doesn't multi-drop at all. This scaling behavior is frequently the deciding factor when speed isn't critical, because pins (and peripheral instance counts) are a hard resource on small MCUs.