How are the stack and heap arranged in SRAM, and what happens if they collide?

The linker lays out SRAM from the bottom: .data (initialized globals, whose values are copied from flash at boot) then .bss (zero-initialized globals, zeroed at boot), then the heap growing upward from there if malloc is used. The stack starts at the top of SRAM and grows downward toward the heap, and the initial stack-pointer value is literally the first word of the vector table. The free gap between the downward-growing stack and the upward-growing heap (or .bss) is the danger zone. If the stack grows far enough to meet the heap, they overwrite each other. The critical point is that a typical Cortex-M has no MMU, so unlike a desktop there's no guard page to fault on overflow, the corruption is silent, manifesting as mangled variables or a crash far from the actual cause. Defenses: size the stack from worst-case call depth plus interrupt nesting, avoid deep recursion and large local arrays, paint SRAM with a sentinel pattern to measure the stack high-water mark, and optionally use the MPU to mark a guard region that faults.