With no clock line, how does the receiver know when to sample each bit?

It recovers timing locally by oversampling. The UART runs an internal clock at a multiple of the baud rate, commonly 16×, so it takes 16 samples per bit period. It watches the idle-high line for the falling edge of the start bit, and from that edge it counts oversample ticks to find the center of each bit (the most stable point, away from the transitions), sampling there and then stepping one bit-time (16 ticks) for each subsequent bit. Some implementations take a majority vote of three samples near the center for noise immunity. Because this sampling free-runs from the single start-bit edge across the whole frame, the receiver's baud clock must match the transmitter's closely, if they differ by more than roughly 2-3%, the accumulated drift moves the sample point off the bit by the last bits of the frame and the data corrupts. That accuracy requirement is the fundamental cost of having no shared clock.