They're placeholders Make fills in per rule invocation so you can write one generic rule instead of one per file. $@ is the target being built, $< is the first prerequisite, and $^ is the complete list of prerequisites (deduplicated). A pattern rule like %.o: %.c says "here's how to build any .o from the matching .c," and its recipe $(CC) $(CFLAGS) -c $< -o $@ uses $< for the specific source and $@ for the specific object, so the single rule handles main.o from main.c, uart.o from uart.c, and so on. For a link rule like firmware.elf: $(OBJS), the recipe uses $^ to pass all the object files to the linker. This matters because without pattern rules and automatic variables you'd duplicate a near-identical rule for every source file, which is verbose and a maintenance hazard, adding a file means adding a rule. With them, you add a file to the OBJS variable and the existing pattern rule and auto-dependencies handle it. So pattern rules plus automatic variables are how a Makefile stays concise and scalable as the project grows.
Debugging & Toolchain · Interview question
What do the automatic variables $@, $<, and $^ mean, and why use pattern rules?
A strong answer
What a weak answer sounds like
You know the answer. Do you know what gets you dinged?
Pro breaks down the answer most candidates actually give to this question — and the specific reason an interviewer marks it down. It’s the difference between sounding correct and sounding senior, on all 472 questions.
From the lesson
The Build Process & Makefiles
Automating compile-and-link and rebuilding only what changed: Make rules (target/prereq/recipe), pattern rules and variables, and auto-generated header dependencies that avoid stale builds.