Explain the GPIO-toggle trick and when you'd use it.

The GPIO-toggle trick is a non-intrusive way to measure timing on real hardware by driving a spare GPIO pin to mark the start and end of a region of interest and observing that pin on a scope or logic analyzer. Concretely, at the entry of an ISR (or critical section, or task) you set the debug pin high, ideally with an atomic single-instruction write like the bit-set register so the marking itself is negligible, and at the exit you clear it; then on the instrument the pulse width equals the region's execution time and the pulse frequency (or the gap between pulses) tells you how often it runs and the idle time between invocations. You'd use it to measure interrupt latency and ISR execution time, to check whether a periodic task is actually meeting its period, to visualize jitter, to find worst-case timing, or to see how two activities overlap (using multiple debug pins to watch task scheduling and contention). Its great advantage is that it's non-intrusive: unlike halting at a GDB breakpoint, which stops the world and changes the very timing you're trying to measure (the Heisenbug problem), toggling a pin perturbs execution by only a couple of instructions, so you observe true real-time behavior, even in the field over long runs. It's cheap (one pin, two register writes), works with the simplest logic analyzer, and is often the only practical way to measure real-time timing accurately. The main caveats are using an atomic write so the marking is cheap and consistent, and reserving a spare pin for it.